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| 74F112 Dual JK Negative Edge-Triggered Flip-Flop April 1988 Revised July 1999 74F112 Dual JK Negative Edge-Triggered Flip-Flop General Description The 74F112 contains two independent, high-speed JK flipflops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J and K inputs can change when the clock is in either state without affecting the flip-flop, provided that they are in the desired state during the recommended setup and hold times relative to the falling edge of the clock. A LOW signal on SD or CD prevents clocking and forces Q or Q HIGH, respectively. Simultaneous LOW signals on SD and CD force both Q and Q HIGH. Asynchronous Inputs: LOW input to SD sets Q to HIGH level LOW input to CD sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH Ordering Code: Order Number 74F112SC 74F112SJ 74F112PC Package Number M16A M16D N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Logic Symbols Connection Diagram IEEE/IEC (c) 1999 Fairchild Semiconductor Corporation DS009472 www.fairchildsemi.com 74F112 Unit Loading/Fan Out U.L. Pin Names J1, J2, K1, K2 CP1, CP2 CD1, CD2 SD1, SD2 Data Inputs Clock Pulse Inputs (Active Falling Edge) Direct Clear Inputs (Active LOW) Direct Set Inputs (Active LOW) Description 1.0/1.0 1.0/4.0 1.0/5.0 1.0/5.0 50/33.3 Input IIH/I IL HIGH/LOW Output I OH/I OL 20 A/-0.6 mA 20 A/-2.4 mA 20 A/-3.0 mA 20 A/-3.0 mA -1 mA/20 mA Q1, Q2, Q1, Q2 Outputs Truth Table Inputs SD L H L H H H H H (h) = HIGH Voltage Level L (l) = LOW Voltage Level X = Immaterial = HIGH-to-LOW Clock Transition Q 0(Q 0) = Before HIGH-to-LOW Transition of Clock Outputs J X X X h l h l K X X X h h l l Q H L H Q0 L H Q0 Q L H H Q0 H L Q0 CD H L L H H H H CP X X X Lower case letters indicate the state of the referenced input or output one setup time prior to the HIGH-to-LOW clock transition. Logic Diagram (One Half Shown) Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 74F112 Absolute Maximum Ratings(Note 1) Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) -0.5V to VCC -0.5V to +5.5V -65C to +150C -55C to +125C -55C to +150C -0.5V to +7.0V -0.5V to +7.0V -30 mA to +5.0 mA Recommended Operating Conditions Free Air Ambient Temperature Supply Voltage 0C to +70C +4.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol VIH VIL VCD VOH VOL IIH IBVI ICEX VID IOD IIL Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current 4.75 3.75 -0.6 -2.4 -3.0 IOS ICCH ICCL Output Short-Circuit Current Power Supply Current Power Supply Current -60 12 12 -150 19 19 mA mA mA Max Max Max mA Max 5.0 7.0 50 A A A V A Max Max Max 0.0 0.0 VIN = 2.7V VIN = 7.0V VOUT = VCC IID = 1.9 A All other pins grounded VIOD = 150 mV All other pins grounded VIN = 0.5V (Jn, Kn) VIN = 0.5V (CPn) VIN = 0.5V (CDn, SDn ) VOUT = 0V VO = HIGH VO = LOW 10% VCC 5% VCC 10% VCC 2.5 2.7 0.5 V Min Min 2.0 0.8 -1.2 Typ Max Units V V V V Min Min VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal IIN = -18 mA IOH = -1 mA IOH = -1 mA IOL = 20 mA 3 www.fairchildsemi.com 74F112 AC Electrical Characteristics TA = +25C Symbol Parameter Min fMAX tPLH tPHL tPLH tPHL Maximum Clock Frequency Propagation Delay CPn to Qn or Qn Propagation Delay CDn, SDn to Qn, Qn 85 2.0 2.0 2.0 2.0 VCC = +5.0V CL = 50 pF Typ 105 5.0 5.0 4.5 4.5 6.5 6.5 6.5 6.5 Max TA = 0C to +70C VCC = +5.0V CL = 50 pF Min 80 2.0 2.0 2.0 2.0 7.5 7.5 7.5 7.5 Max MHz ns Units ns AC Operating Requirements TA = +25C Symbol Parameter VCC = +5.0V Min tS(H) tS(L) tH(H) tH(L) tW(H) tW(L) tW(L) tREC Setup Time, HIGH or LOW Jn or Kn to CPn Hold Time, HIGH or LOW Jn or Kn to CPn CP Pulse Width HIGH or LOW Pulse Width, LOW CDn or SDn Recovery Time SDn, CDn to CP 4.0 3.0 0 0 4.5 4.5 4.5 Max TA = 0C to +70C VCC = +5.0V Min 5.0 3.5 0 0 5.0 ns 5.0 5.0 ns ns Max Units 4.0 5.0 ns www.fairchildsemi.com 4 74F112 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D 5 www.fairchildsemi.com 74F112 Dual JK Negative Edge-Triggered Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com |
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